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4M x 16-Bit Dynamic RAM ( 8k, 4k & 2k Refresh)
HYB 3164160AT(L) -40/-50/-60 HYB 3165160AT(L) -40/-50/-60 HYB 3166160AT(L) -40/-50/-60
Advanced Information
* * * *
4 194 304 words by 16-bit organization 0 to 70 C operating temperature Fast Page Mode operation Performance: -40 tRAC tCAC tAA tRC tPC RAS access time CAS access time Access time from address Read/write cycle time Fast page mode cycle time 40 10 20 75 30 -50 50 13 25 90 35 -60 60 15 30 110 40 ns ns ns ns ns
* *
Single + 3.3 V ( 0.3V) power supply Low power dissipation: -40 HYB3166160AT(L) HYB3165160AT(L) HYB3164160AT(L) 900 756 612 -50 558 468 378 -60 396 324 270 mW mW mW
* * *
* *
7.2 mW standby (TTL) 3.24 mW standby (MOS) 720 W standby for L-version Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh (L-version only) 2 CAS / 1 WE byte control 8192 refresh cycles /128 ms , 13 R/ 9C addresses (HYB 3164160AT) 4096 refresh cycles / 64 ms , 12 R/ 10C addresses (HYB 3165160AT) 2048 refresh cycles / 32 ms , 11 R/ 11C addresses (HYB 3166160AT) 256 msec refresh period for L-versions Plastic Package: P-TSOPII-50 400 mil
Semiconductor Group
1
6.97
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
This device is a 64 MBit dynamic RAM organized 4 194 304 by 16 bits. The device is fabricated on an advanced second generation 64Mbit 0,35m-CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. This DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)160AT to be packaged in a 400 mil wide TSOP-50 package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. The HYB3164(5/6)160ATL parts (L-version) have a very low power sleep mode" supported by Self Refresh. Ordering Information Type
8k-refresh versions: HYB 3164160AT-40 HYB 3164160AT-50 HYB 3164160AT-60 HYB 3164160ATL-50 HYB 3164160ATL-60 4k-refresh versions: HYB 3165160AT-40 HYB 3165160AT-50 HYB 3165160AT-60 HYB 3165160ATL-50 HYB 3165160ATL-60 2k-refresh versions: HYB 3166160AT-40 HYB 3166160AT-50 HYB 3166160AT-60 HYB 3166160ATL-50 HYB 3166160ATL-60 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 400 mil 400 mil 400 mil 400 mil 400 mil DRAM (access time 40 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 400 mil 400 mil 400 mil 400 mil 400 mil DRAM (access time 40 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 P-TSOPII-50 400 mil 400 mil 400 mil 400 mil 400 mil DRAM (access time 40 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 50 ns) DRAM (access time 60 ns)
Ordering Code
Package
Descriptions
Semiconductor Group
2
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
Pin Configuration
P-TSOPII-50 (400 mil) O VCC I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 N.C. VCC WE RAS N.C. N.C. N.C. N.C. A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 . 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS I/O16 I/O15 I/O14 I/O13 VSS I/O12 I/O11 I/O10 I/O9 N.C. VSS . LCAS UCAS OE N.C. N.C. A12/N.C. * A11/N.C.** A10 A9 A8 A7 A6 VSS
* Pin 33 is A12 for HYB 3164160AT(L) and N.C. for HYB 3165(6)160AT(L) ** Pin 32 is A11 for HYB 3164(5)160AT(L) and N.C. for HYB 3166160AT(L) Pin Names
A0-A12 A0-A11 A0-A10 RAS OE I/O1-I/O16 UCAS,LCAS WE Vcc Vss Address Inputs for 8k-refresh version HYB 3164160AT(L) Address Inputs for 4k-refresh version HYB 3165160AT(L) Address Inputs for 2k-refresh version HYB 3166160AT(L) Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply ( + 3.3V) Ground
Semiconductor Group
3
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
TRUTH TABLE
FUNCTION Standby Read:Word Read:Lower Byte Read:Upper Byte Write:Word (Early-Write) Write:Lower Byte (Early-Write) Write:Upper Byte (Early Write) Read-ModifyWrite Fast Page Mode Read (Word) Fast Page Mode Read (Word) 1st Cycle 2nd Cycle
RAS H L L L L L L L L L L L L L L H-L H-L L-HL L-HL
LCAS H-X L L H L L H L H-L H-L H-L H-L H-L H-L H L L L L
UCAS H-X H H L L H L L H-L H-L H-L H-L H-L H-L H L L L L
WE X H H H L L L H-L H H L L H-L H-L X H L H L
OE X L L L X X X L-H L L X X L-H L-H X X X L X
ROW ADD X ROW ROW ROW ROW ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW X X ROW ROW
COL ADD X COL COL COL COL COL COL COL COL COL COL COL COL COL n/a n/a n/a COL COL
I/O1I/O16 High Impedance Data Out Lower Byte:Data Out Upper-Byte:High-Z Lower Byte:High-Z Upper Byte:Data Out Data In Lower Byte:Data Out Upper-Byte:High-Z Lower Byte:High-Z Upper Byte:Data Out Data Out, Data In Data Out Data Out Data In Data In Data Out, Data In Data Out, Data In High Impedance High Impedance High Impedance Data Out Data In
Fast Page Mode 1st Early Write(Word) Cycle Fast Page Mode 2nd Early Write(Word) Cycle Fast Page Mode RMW Fast Page Mode RMW RAS only refresh CAS-before-RAS refresh Test Mode Entry Hidden Refresh (Read) Hidden Refresh (Write) 1st Cycle 2st Cycle
Semiconductor Group
4
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
I/O1 I/O2
I/O16
WE UCAS LCAS
. .
&
Data in Buffer
No. 2 Clock Generator 16
Data out Buffer
16
OE
9
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
Column Address Buffer(9)
9
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
16
Refresh Counter (13) 13 Row 13
512 x16
Address Buffers(13)
13
Decoder 8192
Row
Memory Array 8192x512x16
RAS
No. 1 Clock
Generator
Block Diagram for HYB 3164160AT(L)
Semiconductor Group
5
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
I/O1 I/O2
I/O16
WE UCAS LCAS
. .
&
Data in Buffer
No. 2 Clock Generator 16
Data out Buffer
16
OE
10
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
12
Column Address Buffer(10)
10
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
16
Refresh Counter (12) 12 Row
1024 x16
Address Buffers(12)
12
Decoder 4096
Row
Memory Array 4096x1024x16
RAS
No. 1 Clock
Generator
Block Diagram for HYB 3165160AT(L)
Semiconductor Group
6
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
I/O1 I/O2
I/O16
WE UCAS LCAS
. .
&
Data in Buffer
No. 2 Clock Generator 16
Data out Buffer
16
OE
11
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
11
Column Address Buffer(11)
11
Column Decoder
Refresh Controller
Sense Amplifier I/O Gating
16
Refresh Counter (11) 11 Row
2048 x16
Address Buffers(11)
11
Decoder 2048
Row
Memory Array 2048x2048x16
RAS
No. 1 Clock
Generator
Block Diagram for HYB 3166160AT(L)
Semiconductor Group
7
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
Absolute Maximum Ratings Operating temperature range..............................................................................................0 to 70 C Storage temperature range.........................................................................................- 55 to 150 C Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V Power supply voltage....................................................................................................-0.5V to 4.6 V Power dissipation......................................................................................................................1.3 W Data out current (short circuit)..................................................................................................50 mA Note
Stresses above those listed under Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.
DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V Parameter Input high voltage Input low voltage Output high voltage (LVTTL) Output H" level voltage (Iout = -2mA) Output low voltage (LVTTL) Output L"level voltage (Iout = +2mA) Output high voltage (LVCMOS) Output H" level voltage (Iout = -100uA) Ouput low voltage (LVCMOS) Output L" level voltage (Iout = +100uA) Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
Symbol
Limit Values min. max. Vcc+0.3 0.8 - 0.4 2.0 - 0.3 2.4 -
Unit Note V V V V V V A A 1) 1)
VIH VIL VOH VOL VOH VOL II(L) IO(L)
Vcc-0.2 -2 -2 0.2 2 2
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
Semiconductor Group
8
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
DC-Characteristics (cont'd)
TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V
Parameter Operating Current -40 ns version -50 ns version -60 ns version
(RAS, CAS, address cycling: tRC = tRC min.)
Symbol
refresh version 2k 4k 155 130 105 2 8k 110 90 75 2
Unit Note
ICC1
250 210 170 mA mA mA mA 2) 3) 4)
Standby Current
(RAS=CAS= Vih)
ICC2 ICC3
-40 ns version -50ns version -60 ns version
2
-
RAS Only Refresh Current: -
250 210 170
155 130 105
110 90 75
mA mA mA
2) 4)
(RAS cycling: CAS = VIH: tRC = tRC min.)
Fast Page Mode Current: -40 ns version -50 ns version -60 ns version
(RAS = VIL, CAS, address cycling: tPC=tPC min.)
ICC4
70 60 50 70 60 50 900 200 70 60 50 900 200 mA mA mA A A 2) 3) 4)
Standby Current
(RAS=CAS= Vcc-0.2V)
ICC5 ICC5
900 200
- -
Standby Current (L-Version)
(RAS=CAS= Vcc-0.2V)
ICC6 CAS Before RAS Refresh Current -40 ns version -50 ns version -60 ns version
(RAS, CAS cycling: tRC = tRC min.)
250 210 170 400
155 130 105 400
155 130 105 400
mA mA mA A
2) 4)
Self Refresh Current (L-version only)
(CBR cycle with tRAS>TRASSmin, CAS held low, WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
ICC7
Semiconductor Group
9
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
AC Characteristics (note: 6,7,8) TA = 0 to 70 C,VCC = 3.3 0.3V Parameter
Symbol
AC64-2F
-40 min.
-50
-60 max. -
Unit Note
max. min. - 90
max. min. - 110
Common Parameters
Random read or write cycle time RAS pulse width CAS pulse width RAS precharge time CAS precharge time Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period for 8k-refresh Refresh period for 4k-refresh Refresh period for 2k-refresh Refresh period for L-versions tRC tRAS tCAS tRP tCP tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH 75 40 10 25 10 0 5 0 5 15 10 10 40 5 1 - - - - ns 100k 50 100k 13 - - - - - - 30 20 - - - 30 128 64 32 256 30 10 0 7 0 7 17 12 13 50 5 1 - - - - 100k 60 100k 15 - - - - - - 37 25 - - - 30 128 64 32 256 40 10 0 10 0 10 20 15 15 60 5 1 - - - - 100k ns 100k ns - - - - - - 45 30 - - - 30 128 64 64 256 ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ms
7
tCRP
tT tREF tREF tREF tREF
Read Cycle
Access time from RAS Access time from CAS Access time from column address OE access time Read command setup time Read command hold time Read command hold time referenced to RAS tRAC tCAC tAA tOEA tRCS tRCH tRRH - - - - 20 0 0 0 40 10 20 10 - - - - - - - - 25 0 0 0 50 13 25 13 - - - - - - - - 30 0 0 0 60 15 30 15 - - - - ns ns ns ns ns ns ns ns
11 11 8, 9 8, 9 8, 10 8
Column address to RAS lead time tRAL
Semiconductor Group
10
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
AC Characteristics (cont'd)(note: 6,7,8) TA = 0 to 70 C,VCC = 3.3 0.3V Parameter CAS to output in low-Z Output buffer turn-off delay Output buffer turn-off delay from OE Data to OE low delay CAS high to data delay OE high to data delay
Symbol
AC64-2F
-40 min. 0 - - 0 10 10 - 10 10 - - - 0 - - 0 13 13
-50 - 13 13 - - - 0 - - 0 15 15
-60 max. - 15 15 - - -
Unit Note
max. min.
max. min.
tCLZ tOFF tOEZ tDZO tCDD tODD
ns ns ns ns ns ns
8 12 12 13 14 14
Write Cycle
Write command hold time Write command pulse width Write command setup time tWCH tWP tWCS 5 5 0 10 10 0 5 0 - - - - - - - - 7 7 0 13 13 0 7 0 - - - - - - - - 10 10 0 15 15 0 10 0 - - - - - - - - ns ns ns ns ns ns ns ns
16 16 13 15
Write command to RAS lead time tR WL Write command to CAS lead time tC WL Data setup time Data hold time CAS delay time from Din tDS tDH tDZC
Read-Modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time OE command hold time tR WC tR WD tC WD tOEH 105 55 25 35 5 - - - - - 126 68 31 43 7 - - - - - 150 80 35 50 10 - - - - - ns ns ns ns ns
15 15 15
Column address to WE delay time tAWD
Fast Page Mode Cycle
Fast page mode cycle time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay tPC tCPA tRAS tRHPC 30 - 40 25 - 25 - 35 - 30 - 30 - 40 - 35 - 35 - ns ns ns
8
200k 50
200k 60
200k ns
Semiconductor Group
11
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
AC Characteristics (cont'd)(note: 6,7,8) TA = 0 to 70 C,VCC = 3.3 0.3V Parameter
Symbol
AC64-2F
-40 min.
-50
-60 max. - -
Unit Note
max. min. - - 71 48
max. min. - - 80 55
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle time CAS precharge to WE tPR WC tCPWD 60 40 ns ns
CAS-before-RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time tCSR tCHR tRPC tWRP 5 5 0 5 5 - - - - - 5 5 0 5 5 - - - - - 5 10 0 10 10 - - - - - ns ns ns ns ns
Write hold time referenced to RAS tWRH
Self Refresh Cycle (L-version only)
RAS pulse width RAS precharge time CAS hold time
tRASS
100k - 75 -50 - -
100k - 90 -50 - -
100k - 110 -50 - -
ns ns ns
17 17 17
tRPS tCHS
Capacitance TA = 0 to 70 C,VCC = 3.3 V 0.3 V, f = 1 MHz Parameter Input capacitance (A0 to A11,A12) Input capacitance (RAS, CAS, WE, OE) I/O capacitance (I/O1-I/O8) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 CIO
Semiconductor Group
12
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
Notes:
1) All voltages are referenced to VSS. Vih may overshoot to Vcc + 2.0 V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. 2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less during a fast page mode cycle ( tpc). 5) An initial pause of 100 s is required after power-up followed by 8 RAS-only-refresh cycles, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16) These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in ReadModify-Write cycles. 17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refresh in an evenly distributed manner over the refresh iterval using CBR refresh cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh. If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey after exit from Self Refresh
Semiconductor Group
13
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL
tCRP
V
IH
UCAS LCAS
VIL
tRAD tASR tASC
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tCAH
Column
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
V
Address
AAAAAAA IH AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
VIL
Row
Row
tRCH tRAH tRCS tRRH tAA tOEA
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
V
WE
AAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
V
OE
IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDZC tDZO tODD tCAC tCLZ
Hi Z
tCDD
I/O (Inputs)
V
AAAAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
tOFF tOEZ
AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA
I/O (Outputs) V
V OH OL
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Valid Data Out
Hi Z
tRAC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL1
Read Cycle
Semiconductor Group
14
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL tCAH
Column
tCRP
V
IH
UCAS LCAS
VIL
tRAD tASR tASC
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
V
. Row
Address
IH
Row
VIL
tRAH
V
tWCS t WP
tCWL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tWCH
WE
IH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
tRWL
OE
V AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDS
I/O (Inputs)
V IH VIL
tDH
Valid Data In
OH I/O (Outputs) V OL
V
Hi Z
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
"H" or "L"
WL2
Write Cycle (Early Write)
Semiconductor Group
15
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCSH tRCD tRSH tCAS tRAL
tCRP
V
IH
UCAS LCAS
VIL
tRAD tASR tASC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tCAH
Column
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
Address V AAAAAAAAA Row AAAAAAAAA AAAAAAAAA IL AAAAAAAAA
V AAAAAAAAA IHAAAAAAAAA AAAAAAAAA
. Row
tRAH
V
WE
IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCWL tRWL tWP
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tOEH
V
OE
IH AAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
VIL
tDZO tDZC
I/O (Inputs)
V IH AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA
tODD tDS tOEZ
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA tDH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
VIL
Valid Data
tCLZ tOEA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
I/O (Outputs) V
V OH OL
Hi-Z
Hi-Z
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL3
Write Cycle (OE Controlled Write)
Semiconductor Group
16
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
tRWC tRAS
V
tRP
RAS
IH
VIL V
tCSH tRCD tRSH tCAS tCRP
IH
UCAS LCAS
VIL
tRAH tASR
V
tCAH tASC
tASR
Row
Address
IH AAAA AAAA AAAA
AAAA AAAA AAAA
VIL
Row
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column
tRAD
V
AAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tCWL tAWD
tCWD tRWD
tRWL tWP
WE
AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA
tAA tRCS
V
tOEA
tOEH
AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA
OE
IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDZO tDZC
V
AAAAAAAAAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tDS
tDH
Valid Data in
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
I/O (Inputs)
tCLZ tCAC
tODD tOEZ
AAAAAA AAAAAA Data AAAAAA AAAAAA AAAAAA Out AAAAAA
I/O (Outputs) V OL
V OH
tRAC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
17
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
tRASP
V IH
tRP
RAS
VIL
tPC tRCD
V IH
tCAS
tCP
tCAS
tRHCP tRSH tCAS
tCRP
UCAS LCAS
VIL
tCSH tRAH tASR tASC tCAH
Column
tASC
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
tCAH tASC
tCAH tASR
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA Column AAAAAAAAA AAAAAAAAA AAAAAAAAA
V
Address
IH AAAAA AAAAA AAAAA
VIL
AAAAA AAAAA AAAAA Row AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
Column
Row
tRAD
tRCH tRCH tRCS
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tRCS
V
tRCS
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAA tRRH AAAAAAA
WE
IH AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
VIL
tAA
V IH AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
tCPA tAA tOEA
tOEA
tCPA tAA tOEA tDZC
OE
VIL
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
tDZC tDZO tODD
tDZC
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
tCDD tODD
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA tOFF
tDZO
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tOFF
I/O (Inputs)
V
tODD
tDZO
IH AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
VIL
tCAC tCLZ
tCAC tCLZ
tRAC
OH I/O (Outputs) V OL V
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tOFF
tCAC tCLZ
tOEZ
tOEZ
tOEZ
AAAAA AAAAA AAAAA Valid AAAAA AAAAA Data Out AAAAA AAAAA
AAAAAA AAAAAA AAAAAA Valid AAAAAA AAAAAA Data Out AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA Valid AAAAAA AAAAAA Data Out AAAAAA AAAAAA
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
FPM1
Fast Page Mode Read Cycle Semiconductor Group 18
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
tRAS
V IH
tRP
RAS
VIL
tPC tRCD
V IH
tRSH tCP tCAS tCAS tCRP
tCAS
UCAS LCAS
VIL
tRAH tASR
V IH AAAAA AAAAA
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tRAL tCAH tASC tASC
AAAAAAAAAA AAAAAAAAAA
tCAH tASC
AAAAAAAAAA AAAAAAAAAA
tCAH
tASR
AAAAAAAAA AAAAAAAAA
Address
VIL
Row
AAAAAAAAAA AAAAAAAAAA AAAAAAAAA Column AAAAAAAAAA Column AAAAAAAAAA Column AAAAAAAAA Column AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA
tRAD tWCS
V
tCWL tWCH tWP
tWCS
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
tCWL
tWCS
tCWL tRWL
WE
AAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
tWCH tWCH tWP AAAAAAAAAAAAA tWP AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
VIL
V
OE
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
IH AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDH tDS
I/O (Inputs)
V
AAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA V AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
tDH tDS
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
tDH tDS
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
IL
Valid Data In
Valid Data In
Valid Data In
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
OH I/O (Outputs) V OL
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
V
HI-Z
"H" or "L"
FPM2
Fast Page Mode Early Write Cycle
Semiconductor Group
19
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
tCPWD tCWD
tAWD
tOEA
tCPWD tCWD
tOEA
tCAH
tRWD tCWD
tAWD
tOEA
tCAH
tDZC tCLZ tDZO
tCSH
Column
tASC
tAA
tCAC
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tWP
Data In
tOEH
tOEZ tDH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column Address
tCLZ
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tWP
tOEH
Data In
tDH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tASC
tCWL
tDZC
tCAC tAA
tCAH
tCPA
tCLZ
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tOEH
tWP
Data In
tDH tOEZ tDS
AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tRAL
tRWL tCWL
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tRP
tCRP
tASR
Row
tODD
tCAS
tPRWC tCAS
tRAS
tODD
tOEZ
tAWD
tASC
tCPA tDZC
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tCWL
tCP
tAA
AAAAAA AAAAAA AAAAAA AAAAAA
tODD
tCAS
I/O (Inputs) V IL
Fast Page Mode Read-Modify-Write Cycle
Semiconductor Group
20
OH I/O (Outputs) V
IH
IH
IH
IH
IH
IH
V IL
V IL
V IL
V IL
V
V IL
V
V
V
Address
UCAS LCAS
RAS
V
WE
OE
V
V
OL
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Row
AAAAAAA AAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAA AAAAAAA AAAAAAA
tASR
"H" or "L"
tRAD
tRAH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tRCD
tRCS
tRAC
Data Out
AAAAA AAAAA AAAAA
tDS
Data Out
AAAAA AAAAA AAAAA
tDS
Data Out
AAAAA AAAAA AAAAA
tRSH
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
tRC tRAS
V
tRP
RAS
IH
VIL
tCRP tRPC
V IH
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
UCAS LCAS
VIL
tRAH tASR
tASR
Row
V
Address
IH AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA
AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA
VIL
Row
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
OH I/O (Outputs) V OL
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
V
HI-Z
"H" or "L"
WL9
RAS-Only Refresh Cycle
Semiconductor Group
21
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
tRC tRP
V
tRAS
tRP
RAS
IH
VIL
tRPC tCP
tCSR tCHR tRPC
tCRP
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
V
UCAS LCAS
IH
VIL
tWRP tWRH
V IH AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
WE
VIL
tOEZ
V
OE
IH
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCDD
IH I/O (Inputs) V IL V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tODD
OH I/O (Outputs)VOL V
HI-Z
tOFF
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL10
CAS-Before-RAS Refresh Cycle
Semiconductor Group
22
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
tRC
V
tRC tRP tRAS tRP
tRAS
IH
RAS
VIL
tRCD
V
tRSH tCHR tCRP
UCAS LCAS
IH
VIL
tRAD tASC tASR tRAH
AAAAA AAAAA AAAAA AAAAA
tWRP tCAH tWRH tASR
Row
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Address
V AAAAAAA IHAAAAAAA AAAAAAA
AAAAAAA VIL AAAAAAA AAAAAAA AAAAAAA
AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Row AAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tRCS
WE
V AAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
tRRH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tAA tOEA
OE
V AAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA tDZC
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCDD
tDZO
V
tODD tCAC tCLZ
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
I/O (Inputs)
IH
VIL
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
tOFF tOEZ
Valid Data Out
tRAC
OH I/O (Outputs) V OL
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
V
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
HI-Z
"H" or "L"
WL11
Hidden Refresh Cycle (Read)
Semiconductor Group
23
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
tRC tRP
V IH
tRC tRAS tRP
tRAS
RAS
VIL
tRCD
V IH
tRSH
tCHR
tCRP
UCAS LCAS
VIL
tRAD tRAH tASR
AAAAA
tASC tCAH
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Address
V AAAAAAA IHAAAAAAA AAAAAAA
AAAAAAA VIL AAAAAAA AAAAAAA AAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA Row AAAAA Column AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Row
tWCS
tWCH tWP
tWRP
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tWRH
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
V
WE
AAAAAAAAAAAAAAAAAAA IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA VIL AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
tDS
V
tDH
Valid Data
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
I/O (Input)
AAAAAAAAAAAAAA IH AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA
V IL
OH I/O (Output) V OL
V
HI-Z
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL12
Hidden Refresh Write Cycle
Semiconductor Group
24
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
tRP
V
tRASS
tRPS
RAS
IH
VIL
tRPC tCSR
V
tCHS
tCRP
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
tCP
IH
UCAS LCAS
VIL
tWRP tWRH
V
WE
IH AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
VIL
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
V
OE
IH
VIL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tCDD
IH I/O (Inputs) V IL V
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tODD tOEZ
OH I/O (Outputs) VOL
V
HI-Z
tOFF
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
"H" or "L"
WL13
CAS-before-RAS Self Refresh (Sleep Mode")
Semiconductor Group
25
HYB3164(5/6)160AT(L)-40/-50/-60 4M x 16-DRAM
Package Outlines Plastic Package P-TSOPII-50
(400 mil width, 0.8 mm lead pitch, thin small outline, SMD)
Semiconductor Group
26

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